Improving the performance of LVDS DDR at 200MHz

You're using a global, which is about as low-skew as you get for general logic. Note that ODV accounts for the fact that, when one path might be pegged at the slow corner, other paths just aren't that bad. This can be due to process(two paths next two each other), but also affects in the FPGA like cross-coupling with a completely different signal may slow one signal down, or there may be a slight power-variance. There's really no way to avoid this and you're using the best path. ODV annoys the heck out of me, but I also think it's pretty real. (I always wonder if other vendors model that? It can make Altera devices look slower, where there's obviously big risk for an interface like this if it were ignored.)

The True LVDS does not use a global clock tree, but a dedicated clock tree along the left and right edges that are probably laid out for minimal variance. That's why it can get such a low number.

How much skew can be tolerated? I'm actually surprised you can't get 800Mbps, as that generally seems do-able in what I've seen. But it's getting faster where things start to fall apart. Also, is the board laid out or are you using a device that doesn't have True LVDS?