Honored Contributor
Honored Contributor1) Is the error from an assignment or something? Why does it think there's an entity called *? (If the top-level entity is wrong in Quartus, found in Assignments -> Settings -> General, then it wouldn't go through at all and there would be nothing to do timing analysis on)
2) Why would place-and-route make it faster. 65% routing is a decent estimate. Of course everything is just an estimate. I wouldn't rely on Fmax summary. Besides not being a complete picture(Fmax is only valid if your source and destination clocks are the same, so all cross clock paths are ignored), you can't get detailed analysis. Assuming you have .sdc constraints, launch TimeQuest and run Report All Summaries from the left Task Window(near the bottom). Then go to the Setup Summary report and see the worst domain. Right click on that and Report Timing. From that dialogue box you can get detailed reports on paths and can analyze what's going on. 3) The device's timing models are not final. That will occur in a future version of Quartus based on silicon characterization(that's a pretty new device and I'd make sure you can get some). In general, when they become final you won't even notice, but no guarantees. 4) Synthesis still runs on a .vqm, it's just really fast since there's not a lot for it to do. But it still needs to take that .vqm and translate it into the device to be fit. (And if you turn on Assignments -> Settings -> Analysis & Synthesis -> WYSIWYG Resynthesis, then Quartus will actually break up the .vqm into equations and resynthesize. This generally gives better results.
