I need a low jitter clock mux in logic cells

Hi Hari,

I'm sorry, but my issue here was never resolved to my satisfaction. I ended up reving the board to add clock feedback paths on the PCB, then I use a 2 input PLL as a 2:1 clock mux. I had to forget about the feature requiring 4 inputs to the mux. If you are able to rev the PCB, make sure you fully understand all the constraints about which pins are allowed to feed which kind of clock control block or pll inputs - I ended up having several wasted clock feedback routes because the input pins were un-useable for clock selection.

Hope this helps,

Dave.