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Altera_Forum
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16 years ago

I need a low jitter clock mux in logic cells

In my application, I need to select one of 4 recovered clocks (GXB CRU outputs) to act as timing reference for other PLLs on my system. Quartus 8.1 or StratixII GX won't allow me to use the clock co...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Dave,

I am facing similar problem as you did with clock control block. I need to use a clock mux with dynamic switching. How did you solve your issue? If you have an example, Please post it.

Thanks,

Hari.