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Altera_Forum's avatar
Altera_Forum
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16 years ago

I need a low jitter clock mux in logic cells

In my application, I need to select one of 4 recovered clocks (GXB CRU outputs) to act as timing reference for other PLLs on my system. Quartus 8.1 or StratixII GX won't allow me to use the clock co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

This has been quiet for a while, but I still need to be able to implement a mux in logic that has fixed latency for each of the "data" inputs, and uses my "select" inputs as the actual selects for the mux. Does anyone have ideas of synthesis constraints or verilog coding styles that can give me such a mux?

It turns out that the clkctrl block has some severe limitations that prevent me using it everywhere I need a clock mux.

Thanks,

Dave.