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Altera_Forum
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16 years ago

I need a low jitter clock mux in logic cells

In my application, I need to select one of 4 recovered clocks (GXB CRU outputs) to act as timing reference for other PLLs on my system. Quartus 8.1 or StratixII GX won't allow me to use the clock co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks for the link. A diagram in chapter 16 seems to show a 4 input mux with stable select lines. That's exactly what I want, but I can't seem to get Quartus to give it to me.

I know that the logic mux is not ideal, and I'll be able to get what I need on the next rev of the board, but I've got to get something working now. So any help on synthesis constraints or whatever would be very much appreciated.

Thanks,

Dave.