Honored Contributor
Honored Contributorhttp://www.altera.com/literature/manual/stx_cookbook.pdf?gsa_pos=3&wt.oss_r=1&wt.oss=cookbook
Chapter 16 talks about clock synchronization. They discuss how to build a clock multiplexer in logic cells with minimal jitter. There are also reference examples you can download at : www.altera.com/literature/manual/cookbook.zip Don't know if you have seen this or not yet, but might be a good start. You might have to also work with your timing analysis to break certain paths and restrictions that it might be over-analyzing. It might also be harder if you have logic both before and after the clock mux that need to be in sync with each other, but if you don't life should be easier. Just my .02 Kevin
