I need a low jitter clock mux in logic cells

1 - Do you have any way to adjust the frequency of your reference clock to match the CRU clock? What is your reference clock source?

2 - Do you have any feedback clock paths connected on the PCB?

FPGAs do not make very good crosspoint switches. To this date this has always been the situation with FPGA transceivers. There is no way to use a recovered CRU clock as the reference clock for a transmitter. And the reason for it is specifically jitter. They don't provide a path because the jitter is too high. I'm hoping this changes in upcoming FPGA families.

Now in the video world there is the concept of genlock. Basically what we do is have a tunable reference clock source (VCXO, DDS, etc.). We then use a phase-frequency detector to track the difference between the CRU clock and the reference clock. We can then tune our reference clock to match the frequency of the CRU clock.

Depending on what you have on the board, you might be stuck unless you can rev the board. Now you can spend the time trying to produce a low-jitter mux in logic but I suspect the jitter will still be too high to meet spec.

Jake