Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I need a low jitter clock mux in logic cells

In my application, I need to select one of 4 recovered clocks (GXB CRU outputs) to act as timing reference for other PLLs on my system. Quartus 8.1 or StratixII GX won't allow me to use the clock co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The GXBs are SONET (OC48).

I've tried:

- hand modify the LU to implement the mux (F0 = a, F1 = b, F2 = c, F3 = d) but the Resource Property Editor won't let me move the inputs to different LU ports. Warning about being unable to modify global nets.

- synthesize the Mux structure alone and hand-stitch. Resource property editor still won't let me move the ports.

- put the 4:1 mux into its own design partition, set it to post-fitting (strict) preserve netlist & routing, accept the screwed up port placement, and re-stitch the verilog that instantiates the mux to map the function I want. Quartus still synthesized the mux, and gave me a different instantiation, with clock nets still connected to the select.