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Altera_Forum's avatar
Altera_Forum
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16 years ago

I need a low jitter clock mux in logic cells

In my application, I need to select one of 4 recovered clocks (GXB CRU outputs) to act as timing reference for other PLLs on my system. Quartus 8.1 or StratixII GX won't allow me to use the clock co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

What other methods have you considered for accomplishing your end goal? A clock mux in logic will most likely have high jitter. May I ask what protocol is the data on the GXB receivers?

Jake