Forum Discussion
SyafieqS
Super Contributor
3 years agoDo you mind to post some snippet and of the code and tb?
liyana
New Contributor
3 years agoThis is the code that I use:
module register (clock , r_enable , w_enable, data_in, data_out);
input clock;
input r_enable;
input w_enable;
input [3:0] data_in;
reg [3:0] registerIS;
output reg [3:0] data_out;
always @(posedge clock)
begin
if (w_enable)
registerIS <= data_in;
else if(r_enable)
data_out <= registerIS;
end
endmodule