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KRaut1's avatar
KRaut1
Icon for New Contributor rankNew Contributor
5 years ago

I have created pipeline multiplier and adder schematic in Quartus Prime Lite edition 16.1. During compilation it is giving error "Error (275024): Width mismatch in port "D" of instance "inst12" and type DFF -- source is ""Sum[31..16]""

Other error is: Error (275023): Width mismatch in Sum[31..16] -- source is ""Sum[31..0]" (ID Add32:inst4)" I have named bus "Sum[31..16]" correctly coming to the input B of MUX4X. I don't know why i...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

May I know if you have any updates?

Thanks.

Best regards,

KhaiY

  • KRaut1's avatar
    KRaut1
    Icon for New Contributor rankNew Contributor
    5 years ago

    Sorry, I forgot to reply. The issue has been resolved. Thanks for support.