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Ryan-SEU's avatar
Ryan-SEU
Icon for New Contributor rankNew Contributor
3 years ago

How to use modelsim to do RTL simulation of DDR3 with UniPHY

Hi everyone, Environment : WIN10 64bits, Quartus II 18.1, modelsim-altera 10.5b, cyclone V E 5CEFA9F31I7N, Micron MT41J128M16JT-125*2. I am a FPGA beginner. In my design, I used two Micron DDR3...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Ryan,


Thanks for your feedback.


I'm not sure what is the reason for that but maybe you can perform a burst transfer of 4 and see if there is any different.


What is the ddr3_wr_state signal represent in here?

What is the different between the ddr_wr_count and ddr_wr_count1?