New Contributor
Regular ContributorHi Ryan,
When generating the example design, you can choose either synthesis or simulation or both of them.
Then the Quartus will generate the design accordingly.
For the simulation file, the Quartus will generate a tcl script for each simulator.
The script should has the library for the initialization and calibration flow of the DDR3.
You can run the generated script to test the design.
Regards,
Adzim
New ContributorSupplement: In modelsim, you can see that I correctly store the data according to the timing requirements, the read data is always 0. but the data can be correctly retrieved in the Signaltap test.Do you know the possible reason?
