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Ryan-SEU
New Contributor
New ContributorHow to use modelsim to do RTL simulation of DDR3 with UniPHY
Hi everyone,
Environment : WIN10 64bits, Quartus II 18.1, modelsim-altera 10.5b, cyclone V E 5CEFA9F31I7N, Micron MT41J128M16JT-125*2.
I am a FPGA beginner. In my design, I used two Micron DDR3...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Ryan,
When generating the example design, you can choose either synthesis or simulation or both of them.
Then the Quartus will generate the design accordingly.
For the simulation file, the Quartus will generate a tcl script for each simulator.
The script should has the library for the initialization and calibration flow of the DDR3.
You can run the generated script to test the design.
Regards,
Adzim
Ryan-SEUNew Contributor
New ContributorHi Adzim,
Thanks for your reply!
I already kown that how use modelsim to do RTL simulation of DDR3. In fact, I can directly use the RTL simulation of quartus Nativelink, but I need to revise the of .do files. Just refer to this link：https://www.macnica.co.jp/business/semiconductor/support/faqs/intel/134865/
Regards,
Ryan
