MahdiOccasional Contributor4 years agoSolvedHow to reduce IC delay? Useful resources Hello, I have some basic questions: My design includes a NIOS and an accelerator that is designed by myself. I designed a custom instruction to connect the accelerator and NIOS together. The cus...Show Moreimage1.png89 KBimage.png456 KBEBERLAZARE_I_Intel4 years agoHi,Do you require further assistances?
Recent DiscussionsTiming analysis - long combinational pathQuartusPro 25.3 Crashed after using the Signal Tap Logic AnalyzerDuplicate_hierarchy_depth / duplicate_registerAutomatically added negative node for TDS output doesn't work with Agilex 5Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG