How to put an additional sub circuit to physically different locations in FPGA?

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You can still use Logic Lock and look at the incremental compilation feature.

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Thank you so much for your help.

https://alteraforum.com/forum/attachment.php?attachmentid=14708&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14709&stc=1

Another question is that: I have the placement of my design on chip planner, how can I determine where they are placed physically in FPGA (board) ? Like I know where the pins are physically on the FPGA (board), but I am not sure which corner in the chip planner image is according to which corner of the FPGA physically in the real board.

Hope that I did make the question clear.

Thank you so much!