How to properly constrain generated clock and synchronizer?

With a PLL, that simplifies your .sdc. It should look like this with the info you've now provided:

create_clock -period 40 [get_ports clk_25MHz_i] -name clk_25MHz

derive_pll_clocks

derive_clock_uncertainty

create_generated_clock -source <output clock pin of PLL> -name clk_4_77MHz -divide_by 21 <output pin of clk4_del2 register>

set_false_path -from [get_clocks clk_25MHz] -to [get_clocks clk_4_77MHz ]

derive_pll_clocks has to come before any constraint that uses the clock from the PLL, so your order is wrong. For "output clock pin of PLL" and "output pin of clk4_del2 register", you'll need to use the Name Finder to find the actual names of the pins, accessible from the create_generated_clock dialog box in the Quartus Text Editor. "X8255_top/clk_100MHz" is not correct because that's what you have in your HDL code, which is not the same as the timing netlist used by the timing analyzer.