How to properly constrain generated clock and synchronizer?

At first I'd like to thank you for taking your time. 🙂

Unfortunately I was not able to translate your recommandation into a working .SDC.

The 100Mhz clock in my design is created by a PLL instantiated in the top level module "X8255_top" (Name: clk_100Mhz, Output of the PLL: c0):

    //
    // Instantiate clock generator/PLL
    //
    wire clk_100MHz;
    wire pll_locked;
    X8255_clkgen pll(
        .inclk0(clk_25MHz_i),
        .c0(clk_100MHz),
        .locked(pll_locked) );

This is the .SDC I created:

(Please mind that the clk25/clk100 are asynchronous to the 4.77MHz clock; I added line 11 therefore)

# Constrain clock port clk_25MHz_i
create_clock -period "25.0 MHz" -name clk_25MHz [get_ports clk_25MHz_i]
create_generated_clock -source [get_pins X8255_top/clk_100MHz] -name clk_4_77MHz -divide_by 21 [get_pins clk4_del2]
 
# Automatically apply a generate clock on the output of phase-locked loops (PLLs)
# This command can be safely left in the SDC even if no PLLs exist in the design
derive_pll_clocks
derive_clock_uncertainty
 
# Clocks are unrelated / asynchronous
set_false_path -from [get_clocks clk_25MHz] -to [get_clocks clk_4_77MHz ]

Unfortunately I now get these warnings (shortened to make more readable):

Warning (332174): Ignored filter at X8255_top.sdc(3): X8255_top/clk_100MHz could not be matched with a pin

Warning (332174): Ignored filter at X8255_top.sdc(3): clk4_del2 could not be matched with a pin

Warning (332049): Ignored create_generated_clock at X8255_top.sdc(3): Argument -source is an empty collection

Warning (332174): Ignored filter at X8255_top.sdc(11): clk_4_77MHz could not be matched with a clock

Warning (332049): Ignored set_false_path at X8255_top.sdc(11): Argument <to> is an empty collection

Info (332050): set_false_path -from [get_clocks clk_25MHz] -to [get_clocks clk_4_77MHz]

Warning (332060): Node: X8255_top:x8255|clk4_del2 was determined to be a clock but was found without an associated clock assignment.

Info (13166): Register X8255_top:x825..... is being clocked by X8255_top:x8255|clk4_del2