How to properly constrain generated clock and synchronizer?

Assuming clock_4_77Mhz is a clock that is driving other logic in your design not shown in this code, it would need to be constrained as a generated clock, not a base clock, since it originates inside the device. There should also be a generated clock constraint for clk_100MHz_i since you say it is generated based on clk_25MHz_i. clk_4_77_i is technically not considered a clock by the timing analyzer since it goes into a data input of a register, not a clock pin, but clock_4_77Mhz is a clock. I highly recommend using a PLL to simplify all this.

So here's my best guess (without seeing your whole design) as to what your .sdc should look something like:

create_clock -period 40 [get_ports clk_25MHz_i] -name clk_25MHz

# use derive_pll_clocks if you're using a PLL (which I'd recommend because it simplifies all of this) or:

create_generated_clock -source [get_ports clk_25MHz_i] -multiply_by 4 <input clock pin of clk4_del0 register> -name clk_100MHz_i

create_generated_clock -source <input clock pin of clk4_del2 register> -name clk_4_77MHz -divide_by 21 <output pin of clk4_del2 register>