Forum Discussion
Altera_Forum
Honored Contributor
11 years agoUse SignalTap II and trace the traffic on the Avalon-MM interface you are writing to. Those traces will show you what the transactions look like at the hardware level.
Just because you send eight 8-bit chars to /dev/mem does not mean they show up in the Avalon-MM space as 8-bit writes, they may show up as wider writes (with byte-enables set appropriately). If you want to use standard components, then writing the 8-bit values to RAM, and then programming an Avalon-MM DMA controller to perform a 64-bit read from that same location, and a write to another location may be a suitable solution, i.e., create a Qsys component with RAM, a DMA controller, and your component that requires 64-bit transactions. Another option would be to; create a component that looks like an 8-bit Avalon-MM slave on one side, and a 64-bit Avalon-MM master on the other. Have the 64-bit side generate a 64-bit transaction each time the 8-bit side has accepted 8 x 8-bit writes (eg., when the write-enable occurs for the last of the 8 bytes). But then you'd have to create HDL code, which might be a little too much at this point ... but if you're willing to learn, and this is the appropriate solution, give it a shot. Cheers, Dave