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Altera_Forum
Honored Contributor
9 years agoHow to infer BRAM fan-out
I am doing an OpenCL project of vector multiplication of VecA (M * 1) and VecB (1 * N) which produces a matrix MatC (M * N). I want to use a fan-out design which can support a 2-D processing engine ...
Altera_Forum
Honored Contributor
9 years ago --- Quote Start --- There are some small code snippets in Altera's documents in the sections I mentioned above, but other than that, I do not know of any other public code showing the systolic array design. --- Quote End --- Intel's FPGA systolic array example is a controlled material(using public code may not able to get best performance as not optimized for FPGA), and in the event user wish to have a copy that need to contact Altera representative separately. Regards, CloseCL (This message was posted on behalf of Intel Corporation)