How to generate two non overlapping clock signals from single clock?

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Doing logic with the clock is pretty much a no-no in FPGAs. The skew will just kill it.

Why not just derrive a 2x EXT_CLK using a PLL? You can lock the PLL so that it is in sync with EXT_CLK.

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Thanks for the answers!

The FPGA should connect to an old system that is using a two phase non-overlapping clock and this clock is

too low to be used for the PLL.

Just a last question (for now):

What is better if I want to use both edges of the clock in a design:

1. using always @ (posedge CLK) and always @ (negedge CLK) or

2. using @ (posedge CLK) and @(posedge CLK_n)

3. both variants 1+2 are just equivalent?

Thanks!