Forum Discussion
hzs268
New Contributor
New ContributorHow to fix lut4 input ports?
I need to implement a arbiter puf in cycloneive fpga, with the requirement of extreamly net delay parameter about less than 100ps.
I know that chip planner can change the lut input port in gui di...
SyafieqS
Super Contributor
Super ContributorAlternatively, you should be looking at timing constraint e.g set_net_delay. Use the set_net_delay command to query the net delays
and perform minimum or maximum timing analysis across nets of <0.1ns
hzs268New Contributor
New ContributorThanks a lot SyafieqS!
I tried to lock my design LUT location by 'set_location_assignment' for identical net delay between every PUF mux slice.
The 'set_net_delay' constraint works after I delete the constraint of LUT location, let Quartus fit according to the timing constraint.
Now the net delay between PUF mux slice is very close and achieve my goal.
