How to fix large number of hold violations for Cyclone V GX in Quartus II?

PLL_1|pll_clk_manager_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk is the main PLL derived clock that drives most of the logic in my design. I've attached 120 paths that contain hold violations - there are 375 in total.

In terms of clock skew, TimeQuest reports an average of 0.6ns of clock skew for all the failing paths but also reports 0.6ns of clock skew for paths that do not have hold violations.