how to find Dmin and Dmax

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how we can find maximum and minimum data delay (excluding pin) delay in quartus II ?

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Hi,

are you looking for the delay of a certain path in your design ?

kind regards

GPK

ya ..when we are dealing with wave-pipelining circuit we need to calculate these min and max delay. there will be some output arriving earlier and some output arriving later.. what are those minimum and maximum delays..? For eg. consider any logic with input and output registers.. ; what will be the minimum and maximum propagation delay between those input and ouput registers?

Note: here i want to exclude the pin delay.. ie. from input pin to input reg and from output reg to output pin.

does the tool itself report these report or we need to calculate manually ? if we need to calculate manually wat are the parameters that we can use from tool reporting?

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ya ..when we are dealing with wave-pipelining circuit we need to calculate these min and max delay. there will be some output arriving earlier and some output arriving later.. what are those minimum and maximum delays..? For eg. consider any logic with input and output registers.. ; what will be the minimum and maximum propagation delay between those input and ouput registers?

Note: here i want to exclude the pin delay.. ie. from input pin to input reg and from output reg to output pin.

does the tool itself report these report or we need to calculate manually ? if we need to calculate manually wat are the parameters that we can use from tool reporting?

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Hi roshansilwa,

first of all you have to constrain your design. Set your required fmax and the input and output requirements according to the requirements of the source(s) and destination(s) of the FPGA. The constraints will be used by Quartus in order to insure that the timings will be met . The timing analysis after P&R will show all your required info's.

You can run in Timequest a worst-case (will give you the slowest fmax, longest delays) and a fast timing run (will give you the fastest fmax, shortest delays). As long as Timequest reports no timing violation your FPGA should work in the application.

Kind regards

GPK

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how to constrain the design..? i ve been using only the classing timing ..m new to timing quest analysis..? Could u plz explain bout setting the design constraint and bout timing quest analysis..

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Hi,

what timing constraints did you set in the classic timing analyzer ?

Kind regards

GPK