how to deal with these compilation warnings ?

I get several warnings after full compilation as below:

Warning (332174): Ignored filter at qsta_default_script.tcl(1028): *ws_dgrp|dffpipe_se9:dffpipe16|dffe17a* could not be matched with a clock or keeper or register or port or pin or cell or partition

Warning (332049): Ignored set_false_path at qsta_default_script.tcl(1028): Argument <to> is not an object ID

Info (332050): read_sdc

Warning (332174): Ignored filter at LTE.sdc(8): \ could not be matched with a clock

Warning (287001): Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2

Warning (169064): Following 4 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results

Info (169065): Pin UPP_D[8] has a permanently enabled output enable

Info (169065): Pin UPP_D[9] has a permanently enabled output enable

Info (169065): Pin UPP_D[10] has a permanently enabled output enable

Info (169065): Pin UPP_D[11] has a permanently enabled output enable

I have no idea what problems these warnings will lead to. Can someone make a detail and clear explanation of the meaning of these warnings? So I can deal with them. My sdc file is post below:

set_time_format -unit ns -decimal_places 3

create_clock -name F20M -period 50 [get_ports {F20M}]

create_clock -name SDWE -period 10 [get_ports {SDWE}]

create_clock -name BS_clk -period 32.552 [get_ports {BS_clko1}]

derive_pll_clocks

derive_clock_uncertainty

set_clock_groups -asynchronous

-group {F20M}

-group {SDWE}

-group {BS_clk

PLL1_inst|altpll_component|auto_generated|pll1|clk[0]

PLL1_inst|altpll_component|auto_generated|pll1|clk[1] \

PLL1_inst|altpll_component|auto_generated|pll1|clk[3] \

}

-group {

PLL1_inst|altpll_component|auto_generated|pll1|clk[2]

}

Thanks!

Tigre