Forum Discussion
Altera_Forum
Honored Contributor
13 years agoThere's a few ways you can do this.
1) If your signal is a multiple of 4-bits, then you can use X to indicate hex. signal d : std_logic_vector(15 downto 0) := X"1234"; 2) If your signal is a mixture, you can use a concatenate operator, eg., to set 18-bits to 12345h, you could use signal d : std_logic_vector(17 downto 0) := "01" & X"2345"; 3) Using VHDL-2008 you can use a width specifier signal d : std_logic_vector(17 downto 0) := 18X"12345"; You can also use conversion functions, eg., to convert an integer value in hex format 16#12345# to std_logic_vector. Cheers, Daveedit - fixed the bus widths for you...