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NuvKFC's avatar
NuvKFC
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3 years ago
Solved

How to constraint min delay between LCELLs?

Some asynchronous need to use LCELLs to generate pulses, like following example. However, the delay of LCELLs is different on the difference FPGA device. So, I use following constraints to constr...
NuvKFC's avatar
NuvKFC
Icon for Contributor rankContributor
3 years ago

Hi Nurina
Thank you, Nurina, very much.

I had tried following constraint to limit the min delay between LCELLs to more than 0.8 ns.

But it fail.

After compiling done, I report the path delay in TimeQuest, which is from the LCELLs output to another LCELLs output.

The delay time still small than 0.8 ns.

Constraints:

set_min_delay 0.8 -from [get_pins dly*d|combout] \

-to [get_pins dly*d|data*]

Report command:

report path -from [get_pins dly*d|combout] -to [get_pins dly*d|combout]

Design:

lcell dly1d( .out(Y1), .in(A) );

lcell dly2d( .out(Y2), .in(Y1) );

lcell dly3d( .out(Y3), .in(Y2) );

lcell dly4d( .out(Y4), .in(Y3) );