Forum Discussion
ContributorHow to constraint min delay between LCELLs?
Hi,
Right so I don't think this constraint works on LCELLS alone. Because you would need a setup/hold relationship in the first place.
Which brings us back to using set_data_delay, which definitely should work on LCELL alone.
Since it isn't supported on Quartus II 13.1, I suggest you migrate to Quartus Standard 21.1 as this would have the set_data_delay.
On the other hand, you are using LCELL to generate a pulse to wake up the clocks right? Maybe you could consider using clock control IP: https://www.intel.com/content/dam/support/jp/ja/programmable/support-resources/bulk-container/pdfs/literature/ug/ug-altclkctrl.pdf
Regards,
Nurina
Regular ContributorHi,
Sorry about that, set_data_delay is pretty new in TimeQuest. I think the best you can do is use set_min/max_delay if you want to use LCELL. These two constraints would override default setup and hold relationships so your specification should be able to take place.
You may find this forum thread useful: https://community.intel.com/t5/Programmable-Devices/set-max-delay-vs-set-net-delay/m-p/232670
Regards,
Nurina
NuvKFCHi Nurina
Thank you, Nurina, very much.I had tried following constraint to limit the min delay between LCELLs to more than 0.8 ns.
But it fail.
After compiling done, I report the path delay in TimeQuest, which is from the LCELLs output to another LCELLs output.
The delay time still small than 0.8 ns.
Constraints:
set_min_delay 0.8 -from [get_pins dly*d|combout] \
-to [get_pins dly*d|data*]
Report command:
report path -from [get_pins dly*d|combout] -to [get_pins dly*d|combout]
Design:
lcell dly1d( .out(Y1), .in(A) );
lcell dly2d( .out(Y2), .in(Y1) );
lcell dly3d( .out(Y3), .in(Y2) );
lcell dly4d( .out(Y4), .in(Y3) );
