NuvKFC
Contributor
ContributorHow to constraint min delay between LCELLs?
Some asynchronous need to use LCELLs to generate pulses, like following example.
However, the delay of LCELLs is different on the difference FPGA device.
So, I use following constraints to constr...
Hi,
Right so I don't think this constraint works on LCELLS alone. Because you would need a setup/hold relationship in the first place.
Which brings us back to using set_data_delay, which definitely should work on LCELL alone.
Since it isn't supported on Quartus II 13.1, I suggest you migrate to Quartus Standard 21.1 as this would have the set_data_delay.
On the other hand, you are using LCELL to generate a pulse to wake up the clocks right? Maybe you could consider using clock control IP: https://www.intel.com/content/dam/support/jp/ja/programmable/support-resources/bulk-container/pdfs/literature/ug/ug-altclkctrl.pdf
Regards,
Nurina
