Forum Discussion
ContributorHow to constraint min delay between LCELLs?
Hi,
Right so I don't think this constraint works on LCELLS alone. Because you would need a setup/hold relationship in the first place.
Which brings us back to using set_data_delay, which definitely should work on LCELL alone.
Since it isn't supported on Quartus II 13.1, I suggest you migrate to Quartus Standard 21.1 as this would have the set_data_delay.
On the other hand, you are using LCELL to generate a pulse to wake up the clocks right? Maybe you could consider using clock control IP: https://www.intel.com/content/dam/support/jp/ja/programmable/support-resources/bulk-container/pdfs/literature/ug/ug-altclkctrl.pdf
Regards,
Nurina
Regular ContributorHi,
Is there any reason why you don't want to create a pulse using flip flops? I don't think it's a good idea to create a pulse using LCELL primitive, its delay depends on hardware variables, so race conditions may happen thus creating an unreliable circuit: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/prim/prim_file_lcell.htm
Regards,
Nurina
NuvKFCHi Nurina
Thank you, Nurina, very much.
Using LCELL to create a pulse is an unreliable circuit.
But the original SoC design has a sleep mode that all clocks are closed.
During that mode, I can only use LCELL to create a pulse to wake up clocks.So, I need to constraint the LCELL delay to make the pulse width more robust.
