Forum Discussion
ContributorHow to constraint min delay between LCELLs?
Hi,
Right so I don't think this constraint works on LCELLS alone. Because you would need a setup/hold relationship in the first place.
Which brings us back to using set_data_delay, which definitely should work on LCELL alone.
Since it isn't supported on Quartus II 13.1, I suggest you migrate to Quartus Standard 21.1 as this would have the set_data_delay.
On the other hand, you are using LCELL to generate a pulse to wake up the clocks right? Maybe you could consider using clock control IP: https://www.intel.com/content/dam/support/jp/ja/programmable/support-resources/bulk-container/pdfs/literature/ug/ug-altclkctrl.pdf
Regards,
Nurina
Regular ContributorHello,
Apologies for the late response, I was on vacation.
Can you share your design so that I can reproduce the problem from my machine?
Regards,
Nurina
NuvKFCHi Nurina
Thank you, Nurina, very much. You may enjoy your vacation first^0^.
My design is as follows. I use LCELL to generate a pulse in a module without a clock.
The design will be implemented on the advance node FPGA device, and it can't be modified.
On the advance node FPGA device, the delay of LCELL becomes shorter.
If the slew rate of A is too late, it may cause the generated pulse to fail.
So, I want to constraint the min between A and Y4.
I try to constraint the min delay between LCELLs, but it fail.
Design:
lcell dly1( .out(Y1), .in(A) );
lcell dly2( .out(Y2), .in(Y1) );
lcell dly3( .out(Y3), .in(Y2) );
lcell dly4( .out(Y4), .in(Y3) );
wire pulse = A & ~Y4;
