Forum Discussion
ContributorHow to constraint min delay between LCELLs?
Hi,
Right so I don't think this constraint works on LCELLS alone. Because you would need a setup/hold relationship in the first place.
Which brings us back to using set_data_delay, which definitely should work on LCELL alone.
Since it isn't supported on Quartus II 13.1, I suggest you migrate to Quartus Standard 21.1 as this would have the set_data_delay.
On the other hand, you are using LCELL to generate a pulse to wake up the clocks right? Maybe you could consider using clock control IP: https://www.intel.com/content/dam/support/jp/ja/programmable/support-resources/bulk-container/pdfs/literature/ug/ug-altclkctrl.pdf
Regards,
Nurina
Super ContributorThe data ports are the inputs. You can also look in the post-fit Technology Map Viewer to see these in a schematic view.
NuvKFCHi sstrell
Thank you, sstrell, very much.I change the constraints to which are as follows.
Constraints:
set_min_delay 0.8 -from [get_pins dly*d|combout] \
-to [get_pins dly*d|data*]
set_net_delay -min 0.8 -from [get_pins dly*d|combout] \
-to [get_pins dly*d|data*]
After Quartus compile done, I report the relative path. The report command is as follow.
Report command:
report path -from [get_pins dly1d|combout] -to [get_pins dly4d|combout]
I saw the report. The net delay result isn't extended.
Does there have any problem of constraint setting?
Thank you very much.
