Forum Discussion
ContributorHow to constraint min delay between LCELLs?
Hi,
Right so I don't think this constraint works on LCELLS alone. Because you would need a setup/hold relationship in the first place.
Which brings us back to using set_data_delay, which definitely should work on LCELL alone.
Since it isn't supported on Quartus II 13.1, I suggest you migrate to Quartus Standard 21.1 as this would have the set_data_delay.
On the other hand, you are using LCELL to generate a pulse to wake up the clocks right? Maybe you could consider using clock control IP: https://www.intel.com/content/dam/support/jp/ja/programmable/support-resources/bulk-container/pdfs/literature/ug/ug-altclkctrl.pdf
Regards,
Nurina
Super ContributorThe easiest way is to use the Name Finder, accessed when you use one of the GUI dialog boxes to create a timing constraint. You can access them if you have your .sdc file open in the Quartus text editor (Edit menu -> Insert constraint).
NuvKFCHi sstrell
Thank you, sstrell, very much.The Name Finder find signals of LCELL dly1d as follow picture. Which one is the input of the LCELL dly1d?
Thank you very much.
