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Altera_Forum
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10 years ago

How to constrain the outputs of a Cyclone V ALTLVDS_TX (timing)

Hi everyone, I'm working on an FPGA design with a Cyclone V SoC driving a DAC at 250MS/s (dual-channel, one channel on clock high, one on clock low). The FPGA is speed grade I7, but TimeQuest c...
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Altera_Forum
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10 years ago

Ok, this issue is fixed now. In the original design, all the logic including the SERDES was clocked directly from an input pin. Now I have inserted a PLL with a 1:1 one clock ratio and it works. Strange...

Regards,

Philipp