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Altera_Forum
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13 years ago

How to avoid glitch in combinational logic?

In FPGA design, when we design a combinational logic, there may appear glitch since the time property is not ideal in each components. And sometime glitch may cause problem. But how can avoid glitc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks very much, David.

Sometimes I use combinational logic to make an enable or reset signal for IP core in FPGA, like:

assign enable=a&&b;

assign reset = c||d;

then enable and reset will connect to IP core's enable and reset pin. However, since glitch the IP core may be enabled or reseted in unexpected time. So I use a ff to overcome this:

always @(posedge clk)

begin

enable1<=enable;

reset1<=reset;

end

In this typical case, besides add a flip-flop, another other approach can solve the problem?

Thanks!