Forum Discussion
Altera_Forum
Honored Contributor
18 years agoOK.
My design has only one path that crossing clock domain. Pls see the following source code:
architecture WithoutStrobeOutput of FREQMeasure_PeriodCounterDuringStrobe is
signal s_cnt : integer range 0 to (GEN_T_STROBE_WIDTH * GEN_MAX_TARGET_FREQUENCE);
signal s_counter_clear : std_logic := '1';
signal s_clearstep : std_logic;
begin
counter_clear_gen: process (IN_CLK, IN_STROBE)
begin
if (s_clearstep = '1') then
s_counter_clear <= '0';
elsif(rising_edge(IN_STROBE)) then
s_counter_clear <= '1';
end if;
if(rising_edge(IN_CLK)) then
s_clearstep <= s_counter_clear;
end if;
end process;
counter_operation: process (IN_CLK, s_counter_clear, IN_STROBE)
begin
if (s_counter_clear = '1') then
s_cnt <= 0;
elsif (IN_STROBE = '1') then
if (rising_edge(IN_CLK)) then
s_cnt <= s_cnt + 1;
end if;
end if;
end process;
OUT_COUNTERVALUE <= s_cnt;
end WithoutStrobeOutput; The pre-simulation result as the following picture shows: http://blogimg.chinaunix.net/blog/upfile2/080109112932.jpg The DarkRed codes is where the crossing clock path exist. Could you help me on this issue? P.S. The IN_STROBE & IN_CLK are unrelated clocks. Thanks a lot :)