Forum Discussion
Nurina
Regular Contributor
5 years agoHi,
I'm assuming all your modules are in block design files (.bdf) format. If you just add the module A symbol in your top level file then the place and route should not change.
Regards,
Nurina
Fenchia_studentM0907
New Contributor
5 years agoThanks for your reply。
I design one spi module by using verilog , in my project I need to use two SPI Modules.
I hope the place & route of these two are the same because I hope they have the same timing, but according to my understanding, the bdf file is designed with logic gates, so I think this method maybe not fit my usage situation.