How constraint the output delay from the different clock edge to the same pad?

Hi SyafieqS_Intel

My method is as follows constraints. I create two virtual clock for the out pin. Then set different output delay for those virtual clock on the output pin. And add false constraint to disable non-exist path.

create V1 -period 20 -waveform [0 10]

create V2 -period 10 -waveform [0 5]

set_output_delay -max 10 -clock V1 [get_ports Pad_a]

set_output_delay -min 0.0 -clock V1 [get_ports Pad_a]

set_output_delay -max 5.0 -clock V2 [get_ports Pad_a]

set_output_delay -min 0.0 -clock V2 [get_ports Pad_a]

set_false_path -from [get_clocks Clock_a] -through IP1 to [get_clocks V2]

set_false_path -from [get_clocks Clock_a] -through IP2 to [get_clocks V1]