How can I be sure that the compiler is using the correct top-level entity?

Can switching my top-level entity from a block diagram file (.bdf) to a verilog file (.v) can cause any problems if not done properly?

I started my project off with a block diagram as the top-level entity and decided to switch to a verilog file to make things easier. But after doing this, my circuit is not functioning properly and I'm wondering if it's because I did something wrong. I made the new top-level entity by clicking File -> New... -> Verilog HDL File and I named it the same as my bdf so then I had a file called name.bdf and a file called name.v. I understand that the top-level entity is controlled by going to Assignments -> Device... -> General -> Top-level entity: name, but I don't understand how it knows whether to use name.bdf or name.v. So, I deleted name.bdf from Device Design Files in the Project Navigator. Could this be the source of any problems? How can I be sure that the compiler is using the correct top-level entity?

I am using Quartus II v 5.0.