How are Avalon-MM Pipeline Bridges setup correctly?

Hello,

can anybody explain to me how to use the Avalon-MM Pipeline Bridges correctly? I have a Qsys design with a Nios II processor which connects to several peripherals. The system looks like this:

top.qsys (toplevel Qsys file)

|- Nios II

|- peripherals_1.qsys (another Qsys project which contains some peripherals)

|- Avalon-MM Pipeline Bridge

|- peripheral_1

|- peripheral_2

|- ....

|- peripherals_2.qsys (another Qsys project which contains some peripherals)

|- Avalon-MM Pipeline Bridge

|- peripheral_1

|- peripheral_2

|- ....

I want to use the pipeline stages because of timing issues.

Now there are severals settings which I don't really understand:

- In the project settings of each qsys-project I can select "Limit interconnect pipeline stages to". What does this setting do? Is this the global setting for the number of pipeline stages implemented for each Avalon-MM Pipeline Bridge in this project?

- The Avalon-MM Pipeline Bridge offers the option to enable/disable "Pipeline command signals" and "Pipeline response signals". So if I enable for example the "Pipeline command signals" option will Qsys then implement a pipeline stage for the command signals with the number of pipeline stages equal to the value set in "Limit interconnect pipeline stages to"?

Regards

Martin