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Altera_Forum
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14 years ago

Help!:Error (10327)

Hello there everyone, i'm currently trying to implement XTEA in VHDL using the C code from http://en.wikipedia.org/wiki/xtea. The following is my VHDL code: 


Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
use ieee.numeric_std.all;
entity XTEA is    
Port     (
    clk:in std_logic;
    input: in std_logic_vector(63 downto 0);
    key : in std_logic_vector(127 downto 0);
    Encoder_output,Decoder_output: out std_logic_vector(63 downto 0)
        );
end entity;
architecture rtl of XTEA is
signal k: std_logic_vector(0 to 3);
signal     n:integer:=0;
begin
process(clk,input)
variable z,z_up,z_mid,z_down,z_total,y,y_up,y_mid,y_down,y_total: std_logic_vector (31 downto 0);
variable sum: std_logic_vector (31 downto 0) := x"00000000";
variable delta: std_logic_vector (31 downto 0) := x"9e3779b9";
variable test: std_logic_vector (31 downto 0);
variable natvar : natural;
begin
        --divide the key into 4 parts    
        k(0 downto 0)<=key(127 downto 96);
        k(1 downto 1)<=key(95 downto 64);
        k(2 downto 2)<=key(63 downto 32);
        k(3 downto 3)<=key(31 downto 0);
            
if(rising_edge(clk)) then
    if (n=0) then
        --divide input into y and z
        y:= input(63 downto 32);
        z:= input (31 downto 0);
        --sum:=x"00000000";         -- try take this out later
        elsif (n=32) then
        --for decode:delta is delta*2^5 for 32=(2^5) round 
        sum:=delta(26 downto 0)&"00000";
        end if;
--encode        
if (n <32) then
test:=sum and x"3";
natvar := conv_integer(unsigned(test));
z_total:=(((z(27 downto 0)&"0000") XOR ("00000"&z(31 downto 5)))+z) XOR( sum + k( test  downto test ) );
y:=y+z_total;
            sum:=sum+delta;
y_total:=(((y(27 downto 0)&"0000") XOR ("00000"&y(31 downto 5)))+y) XOR (sum+ k( test downto  test ) );
z:=z+y_total;
            
            Encoder_output<=y&z;    
            
--decode            
elsif(n<64) then
        if(n=32) then
        sum:=delta*32;
        end if; 
        
y_total:=(((y(27 downto 0)&"0000") XOR ("00000"&y(31 downto 5)))+y) XOR (sum+ k(sum(31 downto 11) & 3));
z:=z-y_total;
            sum:=sum-delta;
z_total:=(((z(27 downto 0)&"0000") XOR ("00000"&z(31 downto 5)))+z) XOR(sum + k(sum & 3));
y:=y+z_total;
            Decoder_output<=y&z;
        end if;
            n<=n+1; --counter
    end if;
    
end process;
end rtl;
The problems are bolded. What i'm trying to do is to randomly select one of the 4 parts of key: (the full length of key is 128 bits divided into four 32 bits key, k0,k1,k2,k3). Using the "sum & 3", we can randomly select k0, k1, k2 and k3...i'm a total beginner and i think i have totally violated the type from hexadecimal and natural conversion issue which is used in the std_logic_vector((sum & 3) downto (sum & 3)). is there anyway to solve this?i'm seeing the error:

error (10327): vhdl error at xtea.vhd(48): can't determine definition of operator ""and"" -- found 0 possible definitions

if i were to do k( (sum and 3) downto (sum and 3) ) instead of k( test downto test ) which is what i want...any experts please do help! Thanx for helping in advance!:)

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    sum is 32 bits, x"3" is 4 bits. they must be the same length to perform an and.

    secondly you cannot do the indexing you want, as sum is not an integer, and you cannot perform an and with an integer, you'll have to comvert to std_logic vector first.

    another thing. dont use std_logic_arith and numeric_std in the same file. numeric_std was written to replace std_logic_arith and they both conflict.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi Tricky, Thank you so much for advising! Appreciate it!...you mentioned that it is not possible to do the indexing i want, then is it possbile to do this:

    1) perform AND operation (using std_logic_vector)

    2)then convert std_logic_vector to integer

    3)use it for the index

    or is there any coding alternatives that you know of? Thank you so much for the great help!:) Have a nice day ahead!^^
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    1) perform AND operation (using std_logic_vector)

    --- Quote End ---

    Yes, as long as they are both the same length:

    eg:

    test := sum and x"0003";

    --- Quote Start ---

    2)then convert std_logic_vector to integer

    3)use it for the index

    --- Quote End ---

    yes:

    output <= my_slv( to_integer(unsigned(test) ) downto to_integer(unsigned(test)) );
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi Tricky, thank you so much for your prompt reply ...i have one more question, previously you mentioned that i should not use both unsigned.all library with numeric.all library. so which library i should include/exclude (from my code above) if i need to implement the to_integer along with other arithmetic operations such as addition and so on? Thanx in advance!:)

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    the only libraries you need are these:

    Library IEEE;

    USE IEEE.std_logic_1164.all;

    use ieee.numeric_std.all;

    then you can convert std_logic_vector to integer via the unsigned type.

    eg:

    output <= to_integer( unsigned( some_slv) ) ;

    You cannot do arithmatic on std_logic_vector, you must use the signed/unsigned types instead.

    There is no conv_integer function, you use to_integer instead.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hello again trciky, i'm still facing some errors:

    Error (10327): VHDL error at XTEA.vhd(55): can't determine definition of operator ""+"" -- found 0 possible definitions

    The following is the code and the bolded are the changes done: 

    
Library IEEE;
USE IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity XTEA is    
Port     (
    clk:in std_logic;
    input: in std_logic_vector(63 downto 0);
    key : in std_logic_vector(127 downto 0);
    Encoder_output,Decoder_output: out std_logic_vector(63 downto 0)
        );
end entity;
architecture rtl of XTEA is
signal k: std_logic_vector(0 to 3);
signal     n:integer:=0;
begin
process(clk,input)
variable z,z_up,z_mid,z_down,z_total,y,y_up,y_mid,y_down,y_total: std_logic_vector (31 downto 0);
variable sum: std_logic_vector (31 downto 0) := x"00000000";
variable delta: std_logic_vector (31 downto 0) := x"9e3779b9";
variable test: std_logic_vector (31 downto 0);
variable natvar : integer;
begin
        --divide the key into 4 parts    
        k(0 downto 0)<=key(127 downto 96);
        k(1 downto 1)<=key(95 downto 64);
        k(2 downto 2)<=key(63 downto 32);
        k(3 downto 3)<=key(31 downto 0);
            
if(rising_edge(clk)) then
    if (n=0) then
        --divide input into y and z
        y:= input(63 downto 32);
        z:= input (31 downto 0);
        --sum:=x"00000000";         -- try take this out later
        elsif (n=32) then
        --for decode:delta is delta*2^5 for 32=(2^5) round 
        sum:=delta(26 downto 0)&"00000";
        end if;
--encode        
if (n <32) then
test:=sum and x"00000003";
natvar := to_integer(unsigned(test));
z_total:=(((z(27 downto 0)&"0000") XOR ("00000"&z(31 downto 5)))+z) XOR( sum + k( natvar  downto natvar ) );
y:=y+z_total;          sum:=sum+delta;
y_total:=(((y(27 downto 0)&"0000") XOR ("00000"&y(31 downto 5)))+y) XOR (sum+ k( natvar downto  natvar ) );
z:=z+y_total;
            
            Encoder_output<=y&z;    
            
--decode            
elsif(n<64) then
        if(n=32) then
        sum:=delta*32;
        end if; 
        
y_total:=(((y(27 downto 0)&"0000") XOR ("00000"&y(31 downto 5)))+y) XOR (sum+ k(sum(31 downto 11) & 3));
z:=z-y_total;
            sum:=sum-delta;
z_total:=(((z(27 downto 0)&"0000") XOR ("00000"&z(31 downto 5)))+z) XOR(sum + k(sum & 3));
y:=y+z_total;
            Decoder_output<=y&z;
        end if;
            n<=n+1; --counter
    end if;
    
end process;
end rtl;

    The error begins at the line of z_total which is bolded. Why is summation undefined for this case? am i doing anything wrong? Thanx again for the help!:)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    That is because you cannot add std_logic_vectors together directly. You need to convert them to signed or unsigned type (or just declare them as signed/unsigned in the first place instead of std_logic_vector).

    If they are declared as unsigned, you can leave them as they are. But if you really have to have them as std_logic_vectors, here is an example:

    sum := std_logic_vector( unsigned(sum) - unsigned(delta) );

    Hopefully you'll get the idea.