HDL -vs- schematic entry

I guess that both schematic and HDL are translated into some internal data format.

With HDL you can write your code with different levels of abstraction. If you use a low level of abstraction, HDL coding is no fun at all... At a higher level, it is often not clear how things will be translated into LEs by Quartus (or at least, Quartus has a different opinion than the designer ;-) and it is hard to estimate how many ressources you will need. In schematic design however, it is normally easy to see how Quartus will map this to the LEs. Also in my experience, lpm_counters (or MegaWizard generated ones) are more efficient than counters from VHDL code.

So if you want to optimize the design for area, I would stay with the schematic entry.

Other notes:

- At least with newer Quartus version, there is the option to translate a schematic design into VHDL (File -> Create / Update -> Create HDL File...) So you can than compile your VHDL file to see if there is some magic. There won't be.

- I guess you know the "auto pack register" option? (Did this exist also for FLEX10K? Long ago, I am not sure...)

Regards,

Thomas

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