getting crazy with FSM in VHDL. The FSM runs weird and misbehavior

hallo tricky !

thanks for your reply!

1.sorry that i did not meantioned it clearly, i debug the program in CCS , namly i debug the C code in DSP, for the fpga, i don't know how to debug it like C language. do you know it ? testbench ?

2.yes, i get some infered latched in my process. okay, i will eliminate the latches by giving the signals a default values at the beginning of process.

3.for the inout port, it's a mistake.. should be deleted. because in the top level of my VHDL , i need to use the bidirectional ports to transfer the data. so i divided the inout ports to three signals , input and output and wr_en to control the bidirectional ports.

4. i thought that all the input signals should be assigned to the default state 'Z'.. am i made a mistake ?

5. i need th logic generated clock output as an interrrupt signal for the DSP board.