generated file name vhdl

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Hello guys,

I have this issue. I have in the process declarations 2 varaibles of type FILE :

MODULE(A)

PROCESS(clk)

FILE ei : text IS OUT "ei.txt";

FILE ej : text IS OUT "ej.txt";

begin

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This module is generated in the top level entity several times. Each module has its own ID.

Do you know how to generate a different file name for each module?(something like for the first module ei_1.txt ej_2.txt)

Thanks

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Try this:

signal id_str : string(1 downto 1) := "1";
signal filename : string(8 downto 1) := "ei_" & id_str & ".txt";

if your id is integer input you need to have function to convert it to string