General time constraint questions

For designers with simple clock constraints, they are often able to quickly make constraints without understanding them. But as designs get more complex, they often ignore timing problems(or expect things to not be complicated and refuse to take the time to understand it). I'm sure you're frustrated, but hopefully the pain you're going through now will help a lot in future designs, as static timing analysis is a very important skill.

That makes sense that paths from the non PLL clock to the PLL output would have the tight requirement, considering one is 15/4ths of the other. Note that Quartus isn't doing anything funny to make these paths, and that they exist in the RTL. I'm separating Quartus from SOPC builder when I say that, as it looks like something the SOPC builder is creating is clocked by the non-PLL clock. Can you double-check your system to see if anything is run on that domain? Another option is to do a report_timing -to_clock clk_ff and list a lot of paths(maybe a couple hundred). Right now we're only seeing the registers that transfer to another clock domain, but that will show a lot more paths within that clock domain. It might become quickly apparent that a particular component is being clocked by this clock.