General time constraint questions

What would answer a lot of questions is to see a typical Nios project example with some misc user logic modules and a fully constrained timequest sdc file, but I don't see any sdc files in the installed nios examples.

As I understand it, the timequest GUI is supposed to help mine the info needed to properly create the sdc file, and that the sdc should specify timing commands/constraints so the fitter can do a better job, and also commands/constraints so it can analyze the final fitting correctly. Am I on track here?

Even after reading CH6 (lots of terminology, some confusing typos), it isn't clear which sdc entries are used by the fitter and which are used for analysis, or do they all do both? Am I supposed to have both a fitter and an analysis section for the sdc, two different sdcs, or? Once I have written an sdc, added it to my project files and selected timequest, is the sdc applied automatically for fitting and analysis or do I need to go into timequest every time? We are talking hundreds of registers/pins/cells/etc. How will I know when my design is fully constrained or constrained enough?

kwalts doc shows the generated clocks having names like ..|auto_generated|..., but my generated clocks dont have 'generated' in them. Is something wrong?

One of the first steps is to use create_clock, but the waveform info is discarded before adding to the sdc file. I assume this entry is used by the fitter. Is the waveform info ever used (for timing analysis perhaps?).

My top level is a bdf with a nios symbol and some user logic symbols userlogicA, userlogicB, etc. The nios runs at 90Mhz and the userlogicA block at 50mhz. All my user logic is mostly single-cycle synchronous with a couple of divided clocks thrown in. Under classic timing, the fast model meets timing and the standard model had two violations. Inconsistent behavior led me to use timequest.

I have defined a nios component interface for userlogicA which is an avalon MM slave with some typical signals clock,reset,wr,addr,dataout. Since I have specified in SOPC that userlogicA will use the 50mhz clock, I assume it has placed clock crossing logic between the 50mhz interface and the 90mhz avalon bus. Critical warnings in timequest led me to believe I needed to put synchronizers on those same signals between the interface and userlogicA. The clock domain is the same. This can't be correct.

userlogicA also has some inputs and outputs directly from the 90mhz domain via some nios component gpio interfaces. There are warnings for these too, and I can see that syncronizers on those signals make sense, although they are slow static control and status bits and the way they are used it probably would not matter. I just realized I could go into SOPC and also change the clock assignment for the gpio from 90mhz to 50mhz. Some of those async clock domain warnings should go away.

If I needed to tell timequest to stop nagging me about a signal, or to not do anything special for a chunk of logic, how would I?