Gate-level simulation

Question regarding gate-level sims. When running sims with back-annotated timing, I get all kinds of warnings about setup/hold violations on my synchronization flop (double-registered in the new clock domain). This is expected as the inputs I am synchronizing are asynchronous. However, the violations cause 'X's to propogate through my design causing test case failures. If I use the +notimingchecks option, my test cases pass. Is there a way to waive the timing checks ONLY for my meta flops? I have used a consistent naming scheme so they are readily identifiable. My SDC has false paths for the asynchronous inputs, but this doesn't seem to have been pulled into the quartus-generated SDO.

Any suggestions for how to handle this?