force_type confusion

1. I dont have any experience using JTAG other than as a programmer, so someone else will have to comment.

2. Im refering to HDL testbench.

3. The "enable" would be the tri-state enable input. This basically controls which way data is currently flowing. You cannot have two wires driving a bus. Putting the bus in a high impedance state (Z) allows data to be driven from another net.

4. VHDL and Verilog both have advantages and disadvantages. There are many discussions on the internet. Although I think Verilog is generally more popular, but both can produce the same final circuits, and both can be powerful Verification environments. I still dont really understand what you're doing, or why you're trying to drive a net from 2 sources in verilog - you really wouldnt do this in a real circuit that you write in HDL.

I think you are thinking too much like a software programmer and not a hardware designer.